The present invention relates generally to oscillators and more particularly to an oscillator generating a stable clock signal.
Oscillators are commonly incorporated within various semiconductor devices (e.g., semiconductor memories and/or control logic devices) to generate periodic signals, such as clock signals. Clock signals, a generic term applied to a broad class of reference timing signals, are applied to pump circuits, timing circuits, data latches, etc.
Oscillators generate one or more clock signals in accordance relation to a voltage comparison. For example, a working voltage (or a so-called internal voltage) developed by the charging or discharging of a capacitor may be compared to an externally provided reference voltage. Thus, the amplitude and/or cyclical characteristics of a clock signal will be affected by any variation in a power source voltage applied to the oscillator.
Assuming in one example that a conventional oscillator includes a comparator (e.g., a differential amplifier) comparing an internal voltage with a reference voltage, such a comparator may be activated in response to an enable signal. That is, the comparator begins a voltage comparison operation upon detecting a low-to-high transition in the applied enable signal. However, the rise time of the enable signal transition may become skewed (i.e., may be extended) due to a lower than specified power source voltage. If the low-to-high transition extends into the output timing of the comparator, it may cause difficulty in generating a “normal clock signal” (i.e., a clock signal meeting a defined specification for amplitude, period, and/or phase, etc.).
FIG. 1 is a circuit diagram showing a comparator adapted for use within a conventional oscillator. As shown in FIG. 1, comparator 10 includes PMOS transistors MP1, MP2, and MP3, and NMOS transistors MN1, MN2, and MN3. When the level of power source voltage Vcc falls below a defined operating threshold, comparator 10 may operate in response to an extended low-to-high transition for the first enable signal En and its logical complement second enable signal EnB.
The PMOS and NMOS transistors, MP1 and MN1, activate comparator 10 in response to first and second enable signals EnB and En, respectively. The activated comparator 10 then operates to compare first and second voltages V1 and V2, which are provided respectively through the NMOS transistors MN2 and MN3. The result of the comparison is provided at output terminal Out.
If the first voltage V1 is higher than the second voltage V2, comparator 10 outputs a logically “high” output signal. However, if the first voltage V1 is lower than the second voltage V2, comparator 10 outputs a logically “low” output signal. The output of comparator 10 is determined in large part by the current driving characteristics of the PMOS transistor MP3. However, the current “drivability” of the PMOS transistor MP3 varies with the voltage potential at node “a”. When node “a” is at ground, the source of the NMOS transistor MN2 is connected to ground through the NMOS transistor MN1, there is no drain-source potential difference between the NMOS transistor MN2, and no current flows through the NMOS transistor MN2. Hence, node “a” does not stay at ground, but is set to a voltage level that turns ON the PMOS transistors MP2 and MP3.
In the illustrated example of FIG. 1, it is assumed that the output terminal Out is initially at a low level when comparator 10 is not activated. When comparator 10 is activated and the first voltage V1 is higher than the second voltage V2, the output of comparator 10 transitions from low to high. Thus, the current drivability of PMOS transistor MP3 is reduced. The reduced current drivability of PMOS transistor MP3 has the effect of extending a low-to-high transition time for the output of comparator 10.